High k oxide

ABSTRACT

A technique for producing a thin gate oxide having a relatively high dielectric constant. Embodiments relate to the structure and development of a gate oxide having a thickness of less than 1 nm, having a dielectric constant greater than twenty, and being substantially free of undesired electrical characteristics caused by exposure of the gate oxide to high complementary metal-oxide-semiconductor processing temperatures.

FIELD

Embodiments of the invention relate to semiconductor manufacturing. Moreparticularly, embodiment of the invention relate to the formation of athin, thermally stable, substantially defect-free gate oxide within acomplementary metal-oxide-semiconductor (“CMOS”) device.

BACKGROUND

As CMOS devices continue to decrease in size, the need for smaller gateoxides increases, while the need for a relatively high overall oxidedielectric constant remains. Gate oxides typically consist of acombination of a relatively high k (dielectric constant) dielectric anda relatively moderate k dielectric to produce an overall oxidedielectric constant that is somewhere in between the two. Furthermore,the use of typical oxides, such as zirconium-dioxide (“ZrO₂”) andhafnium-dioxide (“HfO₂”), by themselves is generally undesirable,because volumetric expansion from thermal anneal cycles in semiconductorprocessing can result in the formation of defects in the oxide, causingleakage and reliability problems in the transistor.

Therefore, additives, such as aluminum-trioxide (“Al₂O₃”), are typicallycombined with the oxide to help it remain amorphous during exposure tohigh temperatures in processing. The combination of additives, such asAl₂O₃, and typical oxides, such as ZrO₂ and HfO₂, however, can result inan overall effective dielectric constant (k) that is lower thannecessary to accommodate thinner oxides (<1 nm) required in modern CMOSprocesses. Furthermore, additives, such as Al₂O₃, can possess fixedcharge problems as a result of the bonding configuration between theadditive and the oxide.

Typical gate oxides in modern CMOS processes require a dielectricconstant of at least twenty in order to support a dielectric thicknessof 1 nm or less reliably. Furthermore, gate oxides must be able towithstand deteriorating effects, such as oxygen-deficient defects andthermal instability, caused by exposure to high temperatures duringprocessing.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention are illustrated by way of example and notlimitation in the figures of the accompanying drawings, in which likereferences indicate similar elements and in which:

FIG. 1 is a typical CMOS semiconductor device in which at least oneembodiment of the invention may be used.

FIG. 2 is a graph displaying the dielectric constant of an oxide as afunction of its TiO₂ content, according to one embodiment of theinvention.

FIG. 3 is a flow diagram illustrating a portion of a semiconductorprocess that may be used in conjunction with one embodiment of theinvention.

DETAILED DESCRIPTION

Embodiments of the invention described herein relate to complementarymetal-oxide-semiconductor (“CMOS”) processing. More particularly,embodiments of the invention relate to the creation of a gate oxidebeing sufficiently thin, possessing appropriate physical reliability,and having a suitable dielectric constant so as to be compatible withmodern CMOS processing technology.

FIG. 1 illustrates a CMOS device in which one embodiment of theinvention may be used. The device of FIG. 1 is an inverter, whichconsists of an n-type transistor 105 and a p-type transistor 110. Ineach of the transistors is a gate oxide 115, across which an electricfield is created when a gate voltage is applied to the gate 125 whilethe body 120 is biased at a lower potential than the gate.

The gate oxide in typical modern CMOS devices is less than 1 nm thick,but should also have a dielectric constant greater than twenty in orderto support the electric field applied from the gate to the substrate.Because thinner oxides require less dielectric material than thickeroxides, the dielectric constant (k) should be sufficiently high tocompensate for the thinner dielectric.

The n-type dielectric typically consists of ZrO₂, whereas the p-typedielectric typically consists of HfO₂. In order to achieve thedielectric constant required by a gate oxide of less than 1 nm, high kadditives, such as yttrium-trioxide (“Y₂O₃”), lanthanum-trioxide(“La₂O₃”), and titanium-dioxide (“TiO₂”), are combined with the oxides,ZrO₂ and HfO₂, in one embodiment of the invention. The combineddielectric constant of ZrO₂ or HfO₂ and any one of the above high kadditives is sufficiently high (>20) to support an electric field acrossa gate oxide of less than 1 nm. Furthermore, the above additives aresubstantially free of the fixed charge problems associated withadditives, such as Al₂O₃, when bonded with the oxides.

Other additives in other embodiments of the invention may be used thatcan be bonded with ZrO₂ and HfO₂ without the combination suffering fromfixed charge problems while yielding an overall effective dielectricconstant necessary to support a particular gate oxide thickness.Furthermore, the particular ratio between one of the above additives andthe combined oxide depends upon the dielectric constant that is desiredfor the application and not limited to the embodiment of the inventiondiscussed above.

FIG. 2, for example, is a graph illustrating the effective gate oxide'sdielectric constant as a function of the percentage of TiO₂ combinedwith HfO₂. Advantageously, the relationship between the TiO₂ content andthe gate oxide dielectric constant is substantially linear when TiO₂ iscombined with any one of the oxides, ZrO₂ or HfO₂.

FIG. 3 is a flow diagram illustrating at least some of the processoperations that may be used to carry out one embodiment of theinvention. The particular point in the process in which these operationsare used is dependent upon the particular process being used. Atoperation 301, ZrO₂ and HfO₂ are combined with any one of the additives,Y₂O₃, La₂O₃, and TiO₂, in order to form a gate oxide having a highcrystallization onset and sufficient dielectric constant of at leasttwenty while not displaying the fixed charge problems associated withsome additives, such as Al₂O₃.

In order to avoid oxygen-deficient defects that can result in variousundesirable electrical properties of the gate oxide when used in atransistor, the combination is cured by exposing the gate oxide to a lowoxygen partial pressure anneal at operation 305. The anneal operationexposes the gate oxide to a minimum oxygen ambient atmosphere to curedefects while minimizing interfacial oxide growth, which can happenrapidly at certain atmospheric pressures for high k materials. For theembodiment illustrated in FIG. 3, a partial pressure of <1×10⁻³ Torr isused in order to avoid undesirable oxide leakage and interfacial oxidegrowth. The particular anneal pressure and temperature to be useddepends upon the particular oxide and additive combination used to formthe gate oxide.

At operation 310, the combination is doped with nitrogen in order topromote thermal stability at high temperatures, such as >1000 C, duringCMOS processing. Nitrogen may be introduced to the combination viavarious process techniques, including plasma nitridation, thermalnitrogen anneal containing an ambient, such as nitrogen-hydroxide(“NH₃”), nitrous-oxide (“NO”), nitrous-dioxide (“NO₂”), and nitrogen(“N₂”), and implantation. The particular doping technique as well as theambient to be used with the thermal nitrogen anneal is dependent uponthe needs of the particular semiconductor process being used.

While the invention has been described with reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications of the illustrative embodiments,as well as other embodiments, which are apparent to persons skilled inthe art to which the invention pertains are deemed to lie within thespirit and scope of the invention.

1-7. (canceled)
 8. A process comprising: forming a gate oxide comprisinga combination of a first and second material of a first and seconddielectric constant, respectively, which in combination contribute tothe gate oxide having a dielectric constant greater than twenty;annealing the gate oxide; doping the gate oxide with nitrogen.
 9. Theprocess of claim 8 wherein the gate oxide is annealed by exposing thegate oxide to a low-oxygen ambient atmosphere at a pressure range thatis less than 1×10⁻³ Torr.
 10. The process of claim 9 wherein the gateoxide is doped with nitrogen by a process chosen from a group consistingof plasma nitridation, thermal nitrogen ambient anneal, andimplantation.
 11. The process of claim 10 wherein the nitrogen ambientincludes a compound chosen from a group consisting of NH₃, NO, NO₂, andN₂.
 12. The process of claim 8 wherein the first material is chosen froma group consisting of ZrO₂ and HfO₂.
 13. The process of claim 12 whereinthe second material is chosen from a group consisting of Y₂O₃, La₂O₃,and TiO₂.
 14. The process of claim 13 wherein the gate oxide is dopedwith nitrogen at a temperature that is compatible with conventionalcomplimentary metal-oxide-semiconductor processing.
 15. The process ofclaim 8 wherein the gate oxide is formed within a complimentarymetal-oxide-semiconductor device. 16.-20. (canceled)
 21. A methodcomprising: combining a first and second material to produce an oxidehaving a thickness of less than 1 nm and a dielectric constant greaterthan twenty, the oxide being capable of remaining substantiallyamorphous at complimentary metal-oxide-semiconductor (CMOS) processingtemperatures; curing oxygen-deficient defects within the oxide;thermally stabilizing the oxide.
 22. The method of claim 21 wherein thefirst material is chosen from a group consisting of ZrO₂ and HfO₂. 23.The method of claim 21 wherein the second material is chosen from agroup consisting of Y₂O₃, La₂O₃, and TiO₂.
 24. The method of claim 21wherein the oxygen-deficient defects are cured by introducing asubstantially low oxygen atmosphere to the oxide under a pressure ofless than 1×10⁻³ Torr.
 25. The method of claim 21 wherein the oxide isthermally stabilized by introducing nitrogen to the oxide through aprocess chosen from a group consisting of plasma nitridation, thermalnitrogen ambient anneal, and implantation.
 26. The method of claim 25wherein the thermal nitrogen ambient comprises a compound chosen from agroup consisting of NH₃, NO, NO₂, and N₂.
 27. The method of claim 21wherein the oxide is a gate oxide of a CMOS device.